1. Field of the Invention
The present invention relates generally to memory devices and more particularly to a transistor structure within a memory device and methods of designing and manufacturing transistor structures within memory devices.
2. Background of the Invention
Memory devices comprise a plurality of cells that can be programmed and erased. Each cell typically represents a bit of information and cells are typically arranged into words, where each word comprises a certain number of bits. The cells of conventional memory devices are also often arranged in sectors or blocks. Such devices can then be erased or written to on a sector or block basis.
In a conventional memory device, cells are often arranged into an array, where each cell in the array can be accessed via the appropriate combination of word and bit lines. Decoders are often coupled with the array and configured to drive the associated word and bit lines. These decoders can be referred to as word line and bit line decoders, or as X and Y decoders. The decoders can drive the associated word or bit lines and access the data bits stored in a given cell via transistors interfaced with the word and bit lines. For example, a bit line, or Y decoders can access a given cell via a selected bit line coupled with a Bit Line Transistor (BLT).
A conventional BLT layout structure uses the same size transistors throughout the memory device. But a conventional BLT layout can have problems with loading, especially during programming of the device since many of the cells are written to during programming. The problems can worsen as the size of the memory device is scaled down. BLT loading can become more of an issue as the device is scaled down because a higher number of structures in a given area on the silicon die lead to higher capacitance and/or greater current draw
FIG. 2 is a diagram illustrating a portion of an exemplary memory array 200 that includes two BLTs 202 and 204. It will be understood that, generally, a memory array 200 can contain a plurality of BLTs, but that two BLTs 202 and 204 are shown for convenience. BLTs 202 and 204 can be associated with different sectors within array 200, e.g., sector 0 and sector 128, as shown. Each sector, 0 through 128 can, for example, include one or more BLTs.
In this example, Y-decoder 216 can be connected with BLTs 202 and 204 by a metal bit line 214. The loading of metal bit line 214 can be effected by each of the transistors 202 and 204 that are connected to it. For example, each transistor can add some capacitance to the metal bit line 214. As capacitance increases it can take additional current to drive bit line 214. Further, voltage drops can occur due to this capacitance along metal bit line 214, because of the increased current required to drive the capacitance associate with BLTs 202 and 204. This can, for example, affect the ability of a Y-decoder 216 to drive metal bit line 214. Depending on the design of traditional memory array 200 capacitance of transistor 204 can, for example, slow signals from propagating down metal bit line 214 to subsequent transistors that are further from Y-decoder 216.